[ resume ]

[ Cork, Ireland ]

Portrait of Lucas Pereira

Lucas Pereira | Computer Engineer

Verification engineer with 0+ years of experience across DSP, RISC-V, subsystem verification, and emulation.

pereira.lucasmv@gmail.com | LinkedIn | Resume (PDF) Coming soon

:: About

I started in digital design and verification during my Computer Engineering journey, including FPGA-based work for hyperspectral image compression and early exposure to microelectronics project flows. This foundation led me to ASIC functional verification with focus on architecture, modeling, and verification quality for tapeout readiness.

I worked on DSP verification for photonics, then moved into a customer-facing emulation application engineering role at Cadence, solving customer issues and helping unblock major semiconductor players on complex SoC projects. At Eldorado, I worked on safety-critical IP verification through final GDSII delivery and, in parallel, on RISC-V CPU verification, where I developed an in-house RISC-V Python model and contributed to international collaborations. Currently, I am a Senior Design Verification Engineer at Qualcomm, working on subsystem verification with RISC-V for the latest Snapdragon platforms.

UVM and RISC-V Foundational Associate certified.

:: Experience

Qualcomm

Aug 2024 - Present

Senior Design Verification Engineer

Cork, Ireland

Eldorado Research Institute

Mar 2023 - Aug 2024

Digital IC Verification Engineer

Campinas, Brazil

  • Developed CPU verification plans and UVM testbenches.
  • Implemented Python reference models.
  • Worked daily with Verilog/SystemVerilog, DPI-Python integration, and UVM.
  • Executed verification beyond RTL, including GLS, timing analysis, and power analysis.
  • Worked on safety-critical IP verification through final GDSII delivery.

Cadence Design Systems

Mar 2022 - Mar 2023

Senior Application Engineer

  • Application engineer in emulation/prototyping, supporting complex SoC verification flows.
  • Unblocked major semiconductor players by resolving critical bring-up, compilation, and runtime bottlenecks.
  • Strong hands-on expertise with Palladium and Protium platforms, including Verilog/SystemVerilog and UVM environments.

Eldorado Research Institute

Mar 2020 - Mar 2022

Digital IC Verification Engineer

Campinas, Brazil

  • Verified high-speed ASIC DSP blocks.
  • Drove verification planning and reference model implementation.
  • Developed scripting and UVM-based verification flows.
  • Supported GLS execution, timing analysis, and power analysis.

:: Publications

:: Education

Computer Engineering

2014 - 2018

University of Vale do Itajai

Itajai, SC, Brazil

As a course completion work, I implemented in Xilinx FPGA an accelerator for the prediction step of the CCSDS 123 standard for compression of hyperspectral images.

This project led to a publication at ISCAS 2019.

CI Brasil

Apr 2019 - Feb 2020

Universidade de São Paulo

São Paulo, SP, Brazil

National training program funded by the Brazilian federal government, focused on integrated circuit design education.

:: Skills

:: Certifications

:: In the News